1. Field of the Invention
The present invention relates to a method for manufacturing a liquid crystal display (LCD) device including a thin film transistor (TFT), and more particularly, to a method for protecting the TFT from damage due to radio frequency discharge during dry etching.
2. Discussion of the Related Art
As shown in FIG. 1, a conventional liquid crystal display (LCD) device includes two panels and a liquid crystal layer between them. The first panel (an active panel) includes a plurality of gate lines 70 on a transparent substrate 10, a gate pad 75 at an end of each gate line 70, and a gate shorting bar 76 connecting to each gate pad 75 at an edge portion of the transparent substrate 10. The conventional LCD further includes a plurality of a data lines 80 crossing the gate lines 70 and substantially perpendicular to the gate lines 70, a data pad 85 at an end of each data line 80, and a data shorting bar 86 connecting each data pad 85 at another edge portion of the transparent substrate 10. The conventional LCD further includes a pixel electrode 40 located at an area surrounded by two neighboring gate lines 70 and two neighboring data lines 80, and a thin film transistor TFT 31 connected to the pixel electrode 40 near an intersection of the gate line 70 and the data line 80. The TFT 31 includes a gate electrode 70a extended from the gate line 70, a source electrode 80a extended to form the data line 80, a drain electrode 80b facing the source electrode 80a, and a semiconductor layer 90 between the gate electrode 70a and the source and drain electrodes 80a and 80b.
The second panel (a color filter panel) (not shown), includes a color filter, a black matrix, and a common electrode on a second transparent substrate. Before the first and second panels are joined each other, the gate shorting bar 76 and the data shorting bar 86 are removed by cutting them or etching the transparent substrate 10 along line I--I of FIG. 1.
The gate shorting bar 76 and the data shorting bar 86 are used for anodizing the gate line 70 and gate electrode 70a, or for testing the TFT 31.
A method for manufacturing the active panel of the LCD will be described with reference to FIGS. 2A to 2D showing cross-sectional views along line II--II of FIG. 1.
As shown in FIG. 2A, a metal such as aluminum is deposited on a transparent substrate 10 and patterned to form the gate line 70, the gate electrode 70a extending from the gate line 70, and the gate shorting bar 76. The gate shorting bar 76 generally covers the edge portion of the transparent substrate 10. A gate insulation layer 50, including silicon nitride (SiN.sub.x) or silicon oxide (SiO.sub.x), is formed on the gate electrode 70a and the gate shorting bar 76. A semiconductor layer 90, including amorphous silicon (a-Si), and doped semiconductor layers 92a and 92b, including impurity doped amorphous silicon (n.sup.+ a-Si), are formed sequentially on the gate insulation layer 50. The data line 80, including chromium, is formed on the gate insulation layer 50. The source electrode 80a is formed extending from the data line 80 and in ohmic contact with the doped semiconductor layer 92a, and the drain electrode 80b is formed facing the source electrode 80a and in ohmic contact with the doped semiconductor layer 92b.
Not shown in the cross-sectional view is that the data pad 85 is formed at the end of the data line 80. The data pad 85 is connected to the data shorting bar 86 located on the edge of the transparent substrate 10, as shown in FIG. 1. The data pad 85 and the gate shorting bar 86 can be formed simultaneously with the data bus line 80. Alternatively, they can be formed simultaneously with the gate line 70 and can connect to the data line 80 through a contact hole (not shown) formed in the gate insulation layer 50.
A protection layer 55 including silicon nitride, silicon oxide, or benzo-cyclo-butene (BCB), is deposited covering the transparent substrate 10 and the TFT 31.
A photo-resist layer is coated on the protection layer 55 by a spin coating method. The photo-resist layer is patterned using a mask to form a photo-resist pattern 60 that exposes a portion of the protection layer 55 covering the drain electrode 80b, as shown in FIG. 2B. The edge of the gate shorting bar 76 is exposed even if the gate insulation layer 50, the protection layer 55, and the photo-resist pattern 60 cover the entire surface of the transparent substrate 10. The LCD panel, as shown in FIG. 2B, is placed in an etching chamber. The protection layer 55 is etched along with the photo-resist pattern 60 using a dry etching method in which a gas such as SF.sub.6 or CF.sub.4 is brought to a plasma state using a radio frequency (RF) generator. The Si radical of the exposed part of the protection layer 55 reacts with the plasma gas because the protection layer 55 includes SiN.sub.x, SiO.sub.x, or BCB. A volatile material, such as, SiF.sub.4, results when removing the exposed portion of the protection layer 55 from the surface of the transparent substrate 10.
During the etching process using a radio frequency discharge, the TFTs 31 can be damaged by static electricity resulting from charges stored at an exposed edge of the gate shorting bar 76. Furthermore, after the etching processing is finished, the etched shape can be different from what was intended. For example, as shown in FIG. 2C, the contact hole 37 over the drain electrode 80b does not have the desired shape. Additionally, the photo-resist pattern 60 is not removed entirely, and photo-resist remnants 60' will remain on some portions of the protection layer 55.
An indium tin oxide (ITO) layer is deposited over the protection layer 55 and patterned to form a pixel electrode 40 in contact with the drain electrode 80b through the contact hole 37. However, as shown in FIG. 2D, contact condition of the pixel electrode 40 with the drain electrode 80b is poor because the contact hole 37 does not have the desired shape. Additionally, the pixel electrode 40 does not settle on the protection layer 55 due to the photo-resist remnant 60', so a portion of the pixel electrode can wear off.
Finally, the active panel is cut along line I--I shown in FIG. 1 to remove the portion having the gate shorting bar 76 and data shorting bar 86. The removing method uses either mechanical cutting or etching.